1. Field of Invention
Embodiments exemplarily disclosed herein generally relate to semiconductor devices and methods of fabricating the same, and more particularly, to a phase change memory device and a method of fabricating the same.
2. Discussion of the Related Art
A phase change memory device stores data by using a stable state of a phase change material. The phase change material can stably exhibit one of two states depending upon a temperature applied thereto. After heating the phase change material at a temperature higher than a melting temperature of the phase change material and then cooling it down, the phase change material layer exhibits a substantially amorphous state. After heating the phase change material at a temperature higher than a crystallization temperature and lower than the melting temperature and then cooling it down, the phase change material layer exhibits a substantially crystalline state.
The electrical resistivity of the phase change material layer exhibiting a substantially amorphous state is higher than the electrical resistivity of the phase change material layer exhibiting a substantially crystalline state. Accordingly, the logic state of a memory cell formed of phase change material can be differentiated as either logic 1 or logic 0 by detecting a current that flows through the phase change material layer during a read mode.
A cell of a typical phase change memory device includes one access transistor and one phase change element. FIG. 1 is an equivalent circuit of a cell array in a conventional access transistor-type phase change memory device.
Referring to FIG. 1, an access transistor Tx and a phase change device R are connected between word lines WL and bit lines BL. A gate of the access transistor Tx is connected to the word line WL, its drain is connected to the bit line BL, and its source is connected to the phase change device R.
In the device shown in FIG. 1, a unit cell has a structure similar to that of DRAM. In a case of a NOR cell array structure, the size of a cell may have an 8F2 structure, which is 8 times of a minimum feature size F. However, when using the minimum size access transistor, a sufficient current may not be supplied for phase change. Therefore, a big size transistor of 15 through 20F2 structure is required.
Recently, diode-type access phase change memory devices have been proposed. FIG. 2 is an equivalent circuit of a cell array in a conventional access diode-type phase change memory device.
Referring to FIG. 2, the cell array includes a structure where an access diode Dx and a phase change device R are connected in series between word lines WL and bit lines BL. In this structure, the access diode Dx and the phase change device R are connected in series between the word lines WL and bit lines BL such that the size of a memory cell can be reduced as compared to the size of the memory cell shown in FIG. 1.
FIG. 3A is a plan view of a conventional phase change memory device. FIG. 3B is a sectional view of the conventional phase change memory device, taken along line I-I′ of FIG. 3A.
Referring to FIGS. 3A and 3B, a word line 10 extends toward one direction and is disposed on a semiconductor substrate. A first conductor pattern 12 and a second conductor pattern 14 are sequentially stacked on the word line 10. The word line 10 is typically formed as an impurity diffusion layer having a first conductivity type, and the first conductor pattern 12 and the second conductor pattern 14 are formed as an impurity diffusion layer having a second conductivity type. For example, the word line 10 is formed of an n-type impurity diffusion layer, and the first and second conductor patterns 12 and 14 are formed of a p-type impurity diffusion layer. The word line 10 and the first conductor pattern 12 constitute PN-junction to form a diode.
A bottom electrode 16 is formed on the second conductor pattern 12 and a heater 18 is formed on the bottom electrode 16. A phase change layer 20 and a bit line 22 are formed on the heater 18. The bit line 22 corresponds to the top electrode and extends along a direction perpendicular to the word line 10.
When forming the word line 10 and the bit line 22 having a minimum line width, the area occupied by a unit cell may be two times the minimum line width. Accordingly, this improves the degree of integration as compared to traditional transistors. However, when the area occupied by the PN junction of the word line 10 and the first conductor pattern 12 is F2. As a result, a sufficient current to induce phase change within the phase change layer 20 cannot be applied. Therefore, the degree of integration of the phase change memory device is reduced as the size of cell increases.